W19B(L)320ST/B
9.7 Chip/Sector Erase Waveform
Erase Command Sequence (last two cycles)
Read Status Data
TWC
T
AS
VA
VA
Address
2AAh
SA
555h for chip erase
T
AH
#CE
#OE
T
CH
TWP
TWPH
TSE
#WE
TCS
TDS
T
DH
In
Complete
TRB
Data
30h
55h
Progress
10 for Chip Erase
T
BUSY
RY/#BY
TVCS
VDD
Notes:
1. SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write operation Status”).
2. These waveforms are for the word mode
9.8 #Data Polling Waveform (During Embedded Algorithms)
T
RC
Addresses
VA
VA
VA
ACC
T
T
CE
#CE
#OE
T
CH
T
OE
T
DF
TOEH
#WE
T
OH
Complement
Status Data
High Z
High Z
Complement
Status Data
Valid Data
Valid Data
True
True
DQ7
DQ0-DQ6
T
BUSY
RY/#BY
Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Publication Release Date: March 23, 2004
- 45 -
Revision A2
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