BRIGHT
Microelectronics
Inc.
Flexible Sector-erase Architecture:
64K bytes per sector
Individual sector, multiple sector or bulk erase capability.
Individual or multiple-sector protection is user definable.
Table 2. Sector Definition
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
70000H-7FFFFH
60000H-6FFFFH
50000H-5FFFFH
40000H-4FFFFH
30000H-3FFFFH
20000H-2FFFFH
10000H-1FFFFH
00000H-0FFFFH
Preliminary BM29F040
PIN DESCRIPTION
SYMBOL
A
0
- A
18
A
9
DQ
0
-DQ
7
TYPE
I
I
I/O
NAME AND FUNCTION
ADDRESS INPUTS:
for memory addresses. Addresses are internally
latched during a write cycle.
ADDRESS INPUT:
When A
9
is at 12 Volts the ID mode is accessed. During
this mode A
0
decodes between the manufacturer and device ID′s.
DATA INPUTS / OUTPUTS:
Inputs array data on the fourth
CE
and
WE
cycle during a program command. Inputs commands
WE
to the Command
register when
CE
and
WE
are active. Data is internally latched during the
program cycles. Outputs are from Array and Intelligent Identifier
information. The output pins float to tri-state when the chip is deselected or
the outputs are disabled.
CHIP ENABLE:
Activates the device's control logic, input buffers, decoders
and sense amplifiers.
CE
is active low control;
CE
high deselects the
memory device and reduces power consumption to standby levels.
OUTPUT ENABLE:
OE
is active low control signal. This pin gates the
device
’s
outputs through the data buffers during a read cycle. When
CE
is
low and
OE
is high the outputs are tri-state.
WRITE ENABLE:
Controls writes to the Command state Machine and
memory array.
WE
is active low signal. Addresses and Data are latched
during the rising edge of the
WE
pulse.
DEVICE POWER SUPPLY:
Main power source to the device. It′s value is
5V
±
10% or 5V
±
5%.
GROUND:
The device ground for the internal circuitry.
Table 3
CE
I
I
OE
I
WE
Vcc
GND
-4-
WINBOND [ WINBOND ]
