ADVANCE INFORMATION
Switching Characteristics
(Over the Operating Range)
[11]
WCMC1616V9X
WCMC1616V9X-70
Parameter
Read Cycle
t
RC
t
A A
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK
Write Cycle
[13]
t
WC
t
SCE
t
AW
t
HA
t
S A
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12, 14]
OE HIGH to High Z
[12, 14]
[12, 14]
Min.
70
Max.
Unit
ns
70
10
70
35
5
25
5
25
70
5
25
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW and CE
2
HIGH to Low Z
CE HIGH and CE
2
LOW to High Z
[12, 14]
BLE /BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12, 14]
BLE/BHE HIGH to High-Z
[12, 14]
Address Skew
Write Cycle Time
CE LOW and CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[12, 14]
WE HIGH to Low Z
[12, 14]
70
55
55
0
0
55
55
25
0
25
5
Notes:
11. Test conditions assume signal transition time of 1V/ns or higher , timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ),
and output loading
of the specified I
OL
/I
O H
and 30-pF load cpacitance
12. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
14. High-Z and Low-Z parameters are characterized and are not 100% tested.
Document #: 38-14027 Rev. **
Page 6 of 13
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