ADVANCE INFORMATION
Switching Characteristics
Over the Operating Range
70 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
5
70
60
60
0
0
45
60
45
0
25
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW and CE
2
HIGH to Low Z
CE HIGH and CE
2
LOW to High Z
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
BLE / BHE HIGH to HIGH Z
Address Skew
5
25
0
5
25
70
5
25
10
70
35
70
70
Description
Min.
Max.
CG6264AM
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section..
12. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the write.
14. High-Z and Low-Z parameters are characterized and are not 100% tested.
38-XXXXX
Page - 6 - of 12
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
