ADVANCE INFORMATION
Switching Waveforms
(continued)
Write Cycle 1 (WE Controlled)
ADDRESS
t
SCE
CE
CG6264AM
t
WC
CE2
t
AW
t
SA
WE
t
HA
t
PWE
BHE
/
BLE
t
BW
OE
t
SD
DATA I/O
DON’T CARE
t
HD
VALID DATA
Write Cycle 2 (CE or CE
2
Controlled)
t
WC
ADDRESS
t
SCE
CE
CE2
t
SA
t
AW
t
PWE
t
HA
WE
t
BW
BHE/BLE
OE
t
SD
DATA I/O
DON’T CARE
t
HD
VALID DATA
t
HZOE
Notes:
17. Data I/O is high impedance if OE = V
IH
.
18. If Chip Enable goes INACTIVE and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high-impedance state.
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
38-XXXXX
Page - 8 - of 12
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
