Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
A. C Characteristics : (Ta = 0 to 70°C V = 3.3V 0.3V, V = 0V)
DD
SS
VG36641641B
Unit
Parameter
CAS
Latency
symbol
-7
-8
Min
Max
Min
Max
CLK cycle time
3
2
3
2
tck3
tck2
tAc3
tAc2
tCH
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
CLK to valid output delay
5
6
6
6
CLK high pulse width
CLK low pulse width
CKE setup time
2.5
2.5
2
3
3
2
1
2
1
2
1
2
1
3
0
tCL
tCKS
tCKH
tAS
CKE hold time
1
Address setup time
Address hold time
2
tAH
1
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
CLK to output in low - Z
CLK to output in H - Z
tCMS
tCMH
tDS
2
1
2
tDH
1
tOH
tLZ
3
0
3
2
tHZ
5
6
6
6
CLK to output in Hi - Z without load
Row active to active delay
RAS to CAS delay
tOHN
tRRD
tRCD
tRP
1.8
14
1.8
16
ns
ns
20
20
ns
Row precharge time
20
20
ns
ROW active time
tRAS
tRC
tBDL
tDAL
40
120K
48
120K
ns
ROW cycle time
60
68
ns
Last data in to burst stop
Data - in to ACT(REF) command
1
1
CLK
CLK
1+ tRP
1+tRP
Data - in to precharge
Transition time
tDPL
tT
1
1
2
2
1
1
1
2
2
1
CLK
ns
10
64
10
64
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
tRSC
tPDE
tSRX
tREF
CLK
ns
CLK
ms
Document : 1G5-0127
Rev2
Page7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
