VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
VIS
A.C Characteristics:
Test Conditions: (Ta=0 to 70°C V =3.3V ±0.3V ,V =0V)
DD
SS
AC input Levels(VIH/VIL)
Input rise and fall time
Parameter
2.0/0.8V
1ns
Input timing reference level/
Output timing reference level
1.4V
Output load condition
50pF
CAS
VG3617801CT
Unit
Latency
symbol
-8H
-8L
-10
Min
Max
Min
10
Max
Min
10
Max
CLK cycle time
3
2
3
2
tCk3
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCk2
tAC3
tAC2
tCH
13
15
CLK to valid output delay
6
6
6
7
8
8
CLK high pulse width
CLK low pulse width
CKE setup time
3
3
4
tCL
3
3
4
tCKS
tCKH
tAS
3
3
3
CKE hold time
1
1
1
Address setup time
Address hold time
2
2
3
tAH
1
1
1
Data input setup time
Data input hold time
Command setup time
Command hold time
Output data hold time
CLK to output in low-Z
CLK to output in Hi-Z
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
tDS
2
2
3
tDH
1
1
1
tCMS
tCMH
tOH
2
2
3
1
1
1
3
3
3
tLZ
0
0
0
tHZ
3
20
8
3
20
8
3
20
8
tRRD
tRCD
tRP
20
20
26
20
20
26
tRAS
tRC
tBDL
tDAL
50
120,000
50
120,000
60
120,000
ROW cycle time
70
70
86
Last data in to burst stop
1 CLK
1CLK+tRP
1 CLK
1CLK+tRP
1 CLK
1CLK+tRP
Data-in to ACT(REF)
Command (Auto Precharge)
Data-in to precharge
tDPL
tT
1 CLK
1 CLK
1 CLK
ns
ns
ns
ns
ns
ms
Transition time
1
10
32
1
10
32
1
10
32
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
tRSC
tPDE
tSRX
tREF
2 CLK
2 CLK
2 CLK
8
8
8
8
8
8
Document:1G5-0133
Rev.1
Page6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
