128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
Master Clock:
CLK
CKE
Input
Input
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
/CS
Input
Input
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
A0-11
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
BA0,1
Input
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Data In and Data out are referenced to the rising edge of CLK.
Input / Output
Din Mask / Output Disable:
DQM(x4,x8),
DQMU/L(x16)
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Input
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ,VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
JULY.2000
Rev.2.2
Page-4
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
