THCV231-Q_THCV236-Q_Rev.2.60_E
Pin Description
Pin Description for THCV231-Q
Pin Name
TXP
TXN
TCMP
TCMN
GPIO4
Pin No.
Type
CO
CO
CB
CB
B
Description
High-Speed CML Signal Output (Main-Link)
High-Speed CML Signal Output (Main-Link)
CML Signal Bidirectional Input/Output (Sub-Link)
CML Signal Bidirectional Input/Output (Sub-Link)
GPIO4 : General Purpose Input/Output.
When GPIO4 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO4 is used as push pull output, no external
component is required.
29
30
27
28
8
LATEN : Latch select input under Field BET (Sub-
Link)
0 : Forbidden
1 : Latched result
GPIO3
7
B
GPIO3 : General Purpose Input/Output.
When GPIO3 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO3 is used as push pull output, no external
component is required.
SCL
SDA
CLKIN
D11-D0
6
5
13
B
B
I
SCL input/output for 2-wire serial I/F.
SDA input/output for 2-wire serial I/F.
Clock Input
23,22,20-17,15,14,12-
I
Pixel Data Input
9
HSYNC
VSYNC
RF/BETOUT
25
24
4
I
I
B
HSYNC Input
VSYNC Input
RF : Input Clock Triggering edge select. See Figure 17.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output when Field BET
mode.
PDN
1
IL
Power Down
0 : Power Down
1 : Normal Operation
TEST2
TEST1
3
2
I
IL
Test pin. Must be tied to Ground for normal operation.
Test pin. Must be tied to Ground for normal operation.
CAPOUT
CAPINA
26
31
PWR Decoupling Capacitor Pin, 1.2V output.
PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
CAPINP
32
PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
VDD
AVDD
EXPGND
16
21
33
PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
PWR 1.7-3.6V Analog Power Supply Pin for LDO
GND Exposed Pad Ground. Must be tied to the PCB ground
plane through an array of vias.
CO : CML Output buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
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