THCV231-Q_THCV236-Q_Rev.2.60_E
D25/GPIO4
D24/GPIO3
D23-D0
19
B
B
O
D25 : Pixel Data Output
GPIO4 : General Purpose Input/Output when SUBMODE=0,
MSSEL=1 and RXDEFSEL=0.
When GPIO4 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO4 is used as push pull
output or input, no external component is required.
D24 : Pixel Data Output
GPIO3 : General Purpose Input/Output when SUBMODE=0,
MSSEL=1 and RXDEFSEL=0.
When GPIO3 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO3 is used as push pull
output or input, no external component is required.
Pixel Data Output
20
21-24,27-31,33-
39,42-47,52,53
DE
51
50
48
63
O
O
O
DE Output
HSYNC Output
VSYNC Output
Output Enable
HSYNC
VSYNC
OE
IL
0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,
LOCKN when PDN1=0 and except for BETOUT when BET=1
1 : LVCMOS Output Enable
BET
64
6
IL
B
Field BET entry
0 : Normal Operation
1 : Field BET Operation
RF : Output Clock Triggering edge select. See Figure 18.
0 : Falling Edge
RF/BETOUT
1 : Rising Edge
BETOUT : Field BET Result Output
Internal Register Default Setting Select. See Table 36, Table 37
0 : for THCV231-Q
1 : for THCV235-Q
Low Frequency mode select
RXDEFSEL
LFSEL
62
3
I
I
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
Forbid setting 1 when connecting with THCV231-Q.
Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
Main-Link Power Down
PDN1
PDN0
2
1
IL
IL
0 : Power Down
1 : Normal Operation
TEST2
TEST1
5
4
I
IL
Test pin. Must be tied to Ground for normal operation.
Test pin. Must be tied to Ground for normal operation.
CAPOUT
CAPINA
VDD
AVDD
EXPGND
56
59
PWR Decoupling Capacitor Pin, 1.2V output.
PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
PWR 1.7-3.6V Analog Power Supply Pin for LDO
GND Exposed Pad Ground. Must be tied to the PCB ground plane
through an array of vias.
49,41,32,25,16
40
65
CI : CML Input buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
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THine Electronics, Inc.
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