DS_8430_001
78Q8430 Data Sheet
6.5.2 PAUSE Watermark........................................................................................................30
6.5.3 Headroom Watermark ...................................................................................................30
6.6 Counters.....................................................................................................................................30
6.6.1 Summary of Counters....................................................................................................30
6.6.2 Reading and Setting Counter Values ............................................................................31
6.6.3 Precision Counting.........................................................................................................32
6.6.4 Rollover Interrupts .........................................................................................................32
6.7 Packet Classification..................................................................................................................32
6.7.1 Address Filtering............................................................................................................34
6.7.2 Configuring the CAM .....................................................................................................38
6.7.3 Frame Format ................................................................................................................39
6.7.4 Default CAM Rule Summary..........................................................................................39
6.8 Timers ........................................................................................................................................44
6.8.1 PAUSE Timer.................................................................................................................44
6.8.2 HNR Timer.....................................................................................................................44
6.8.3 Interrupt Delay Timer.....................................................................................................44
6.9 EEPROM Controller...................................................................................................................44
6.10 Ethernet MAC ............................................................................................................................44
6.10.1 MAC Transmit Block......................................................................................................44
6.10.2 MAC Receive Block.......................................................................................................45
6.10.3 MAC Control Register....................................................................................................45
6.10.4 Transmitting a Frame.....................................................................................................45
6.10.5 IEEE 802.3 Transmit Protocols......................................................................................45
6.10.6 Transmit Operation........................................................................................................46
6.10.7 Receiving a Frame.........................................................................................................46
6.10.8 Strip Padding/FCS.........................................................................................................47
6.11 MAC Error Reporting .................................................................................................................47
6.11.1 MAC Transmit Errors.....................................................................................................47
6.11.2 MAC Receive Errors......................................................................................................48
6.12 PHY Operations.........................................................................................................................49
6.12.1 Automatic MDI/MDIX Cable Crossover Configuration...................................................49
6.12.2 100Base-TX Transmit....................................................................................................49
6.12.3 100Base-TX Receive.....................................................................................................49
6.12.4 10Base-T Transmit ........................................................................................................49
6.12.5 10Base-T Receive .........................................................................................................50
6.12.6 SQE Test .......................................................................................................................50
6.12.7 Polarity Correction .........................................................................................................50
6.12.8 Natural Loopback...........................................................................................................50
6.12.9 Auto-Negotiation............................................................................................................51
6.12.10 LED Indicators..............................................................................................................51
6.12.11 PHY Interrupts..............................................................................................................51
6.12.12 Internal Clock PLL........................................................................................................51
7
Register Descriptions.......................................................................................................................52
7.1 Register Overview......................................................................................................................52
7.2 QUE Register Overview.............................................................................................................53
7.3 CTL Register Overview..............................................................................................................54
7.4 Snoop Address Space Overview...............................................................................................55
7.5 QUE Registers...........................................................................................................................56
7.5.1 Packet Control Word Register .......................................................................................56
7.5.2 Packet Size Register .....................................................................................................56
7.5.3 Setup Transmit Data Register .......................................................................................57
7.5.4 Transmit Data Register..................................................................................................57
7.5.5 Receive Data Register...................................................................................................57
7.5.6 QUE First/Last Register.................................................................................................58
7.5.7 QUE Status Register .....................................................................................................58
7.6 CTL Registers............................................................................................................................59
7.6.1 DMA Control and Status Register..................................................................................59
7.6.2 Receive Packet Status Register....................................................................................59
Rev. 1.2
3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
