78P2351R 155Mbps NRZ to CMI Converter
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sub-Address
SA[1]
Bit 1
Bit 0
Read/
Write
Port Address
Assignment
PA[3]
PA[2]
PA[1]
PA[0]
SA[2]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Reg.
Sub
Description
Master Control
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Name
MSCR
--
<0>
--
<0>
--
<X>
--
<0>
--
<0>
--
<X>
--
<0>
--
<1>
--
<X>
CKSL[1] CKSL[0]
--
<X>
--
<0>
--
<X>
--
<X>
--
<1>
--
<X>
SRST
<0>
--
<1>
--
<0>
0
1
2
(R/W)
<X>
--
<X>
--
--
(R/W)
--
<0>
--
<0>
--
Reserved
(R/W)
<X>
<X>
b) PA[3:0] = 1 : Port-Specific Registers
Reg.
Sub
Description
Mode Control
Signal Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Name
MDCR
PDTX
<0>
--
PDRX
<0>
--
--
<0>
LOSOR
<0>
--
SMOD[1] SMOD[0]
MON
<0>
--
<0>
--
<0>
BST[1]
<0>
--
--
<0>
--
<0>
TPK
<0>
BST[0]
<0>
--
--
<1>
FRST
<0>
TXEQ
<0>
0
(R/W)
<X>
RLBK
<0>
--
<0>
--
<0>
--
<X>
LLBK
<0>
--
<0>
--
<1>
--
SGCR
(R/W)
ACR1
(R/W)
ACR0
(R/W)
1
<0>
--
<0>
--
Advanced Tx
Control 1
2
<0>
--
<0>
--
<0>
--
--
Advanced Tx
3
Control 0
<1>
--
<0>
--
<1>
--
<0>
--
--
4
Reserved
(R/W)
<1>
--
<X>
--
<X>
--
<0>
RXLOS
<X>
<0>
RXLOL
<X>
<0>
--
<X>
<0>
TXLOL
<X>
<0>
STAT
(R/C)
FERR
5
Status Monitor
Reserved
<X>
<X>
<X>
<X>
6-7
--
--
--
--
--
--
--
--
--
7