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78P2351R-IM/A04 参数 Datasheet PDF下载

78P2351R-IM/A04图片预览
型号: 78P2351R-IM/A04
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom IC,]
分类和应用:
文件页数/大小: 29 页 / 342 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78P2351R 155Mbps NRZ to CMI Converter  
The outputs of the data comparators are connected  
to the clock recovery circuits. The clock recovery  
system employs a digital PLL, which utilizes a line-  
rate reference frequency derived from the clock  
applied to the CKREFP/N pins. After the clock and  
data have been recovered, the data is converted to  
binary by the CMI decoder. NRZ data is transmitted  
through LVPECL drivers at the SODP/N pins.  
FUNCTIONAL DESCRIPTION  
The 78P2351R contains all the necessary transmit  
and receive circuitry for connection between  
155.52Mbit/s NRZ data sources (STS-3/STM-1) and  
CMI encoded electrical interfaces. The 78P2351R  
system interface mimics a 3.3V optics module and  
only requires a reference clock and wideband  
transformer to complete the electrical interface. The  
chip can be controlled via control pins or serial port  
register settings.  
Receiver Monitor Mode  
The SCK_MON pin or MON register bit puts the  
receiver in monitor mode and adds approximately  
20dB of flat gain to the receive signal before  
equalization. Rx Monitor Mode can handle 20dB of  
flat loss typical of monitoring points with up to 6dB of  
cable loss. Note that Loss of Signal detection is  
disabled during Rx Monitor Mode.  
In hardware mode (pin control) the SPSL pin must  
be low. Additionally, the following unused pins  
must be set accordingly:  
SDO pin must be tied low  
SDI pin must be tied low  
SEN pin must be tied high  
Loss of Signal Detect  
The 78P2351R includes an ITU-T G.783 compliant  
Loss of Signal (LOS) detector. When the received  
signal is less than approximately 18dB below  
nominal for 80 UI, the LOS pin is asserted. The  
LOS signal is cleared when the received signal is  
greater than approximately 17dB below nominal for  
80 UI. During LOS conditions, the receive data  
outputs are squelched and held at logic ‘0’.  
In software mode (SPSL pin high), control pins set  
register defaults upon power-up or reset. The  
78P2351R can then be configured via the 4-wire  
serial control interface. See Pin Descriptions  
section for more information.  
REFERENCE CLOCK  
The 78P2351R requires a reference clock supplied  
to the CKREFP/N pins. For reference frequencies of  
19.44MHz or 77.76MHz, the device accepts a single  
ended CMOS level input at CKREFP (CKREFN tied  
to ground). For reference frequency of 155.52MHz,  
the device accepts a differential LVPECL clock input  
at CKREFP/N. The frequency of this reference input  
is selected by either the CKSL control pin or register  
bit as follows:  
Note: Loss of Signal detection is disabled during  
Local Loopback and Receive Monitor Modes.  
TRANSMITTER OPERATION  
The transmitter section generates an adjustable  
G.703 compliant analog signal for transmission  
through a center-tapped transformer onto 75Ω  
coaxial cable. Serial NRZ data is input to the  
78P2351R on the SIDP/N pins at LVPECL levels  
and passed to a low jitter clock and data recovery  
Reference  
CKSL[1:0] bits  
CKSL pin  
Frequency  
19.44MHz  
77.76MHz  
155.52MHz  
Low  
Float  
High  
0 0  
1 0  
1 1  
circuit.  
An optional clock decoupling FIFO is  
provided to decouple the on chip and off chip clocks.  
The NRZ data is encoded to CMI to ensure an  
adequate number of transitions.  
RECEIVER OPERATION  
Each of the transmit timing modes can be configured  
in HW mode or SW mode as shown in the table  
below.  
The receiver accepts G.703 compliant CMI encoded  
data at 155.52Mbit/s from the RXP/N inputs. When  
transformer-coupled to the line, the receiver can  
handle over 15dB of cable loss. The receive jitter  
tolerance is compliant with all relevant standards  
even with 12.7dB worth of cable attenuation and  
inter-symbol interference (ISI). See Receiver Jitter  
Tolerance section for more info.  
The CMI signal first enters an AGC and a high  
performance adaptive equalizer designed to  
overcome inter-symbol interference caused by long  
cable lengths. The variable gain differential amplifier  
automatically controls the gain to maintain a  
constant voltage level output regardless of the input  
voltage level.  
HW Control  
CKMODE  
SW Control  
SMOD[1:0]  
Tx Mode  
Reserved  
Low  
0 0  
1 0  
Synchronous  
Floating  
(FIFO enabled)  
Plesiochronous  
Loop-timing  
High  
n/a  
0 1  
1 1  
4