78P2351R 155Mbps NRZ to CMI Converter
REGISTER DESCRIPTION (continued)
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and
the read/write operation will be ignored.
ADDRESS 1-0: MODE CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Transmitter Power-Down:
7
PDTX
R/W
0
0 : Normal Operation
1 : Power-Down. CMI Transmit outputs are also tri-stated.
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
6
5
PDRX
--
R/W
R/W
0
0
Reserved.
Serial Mode Interface Selection:
SMOD[1] SMOD[0]
0
1
0
0
0
1
Reserved
4
3
SMOD[1]
SMOD[0]
R/W
R/W
X
X
Synchronous data is passed through the CDR and
then through the FIFO.
Plesiochronous data is passed through the CDR to
recover a clock, but the FIFO is bypassed because
the data is not synchronous with the reference clock.
Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit section.
The transmit data is passed through the CDR, but the
FIFO is bypassed.
1
1
Note: Default values depend on the CKMODE pin setting upon reset or
power up.
Receive Monitor Mode Enable:
2
MON
--
R/W
R/W
0
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization.
1:0
01
Reserved.
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
