78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
On the transmit side, when the ENDEC pin is low,
NRZ input data is encoded to Positive and Negative
logic data following the B3ZS (for DS3/STS-1) or
HDB3 (for E3) substitution codes. The NRZ data is
input to the TPOS pin as shown below.
TRANSMIT MONITOR
The transmit monitor function detects activity on the
transmitter output at the LOUTP and LOUTN pins.
When there is a transmitter fault, as in an open or
short on the chip, the transformer, or the circuit
board, the transmit signal amplitude will be altered.
The transmit monitor detects the amplitude of the
driven signal.
The TXOK pin goes low when the amplitude of the
transmit signal is outside a valid amplitude range for
longer than a specified duration. Alternately, the
TXNW bit in the Status Monitor register can be used
to monitor the transmit amlitude.
ENDEC
TPOS
TNEG
1
0
Positive AMI
NRZ data
Negative AMI
‘Don’t Care’
The ENDEC bit in the Mode Control Register can
also control the ENDEC. The Register Control bit
(REGEN) must be enabled if using the register
settings to avoid conflict with external setting pins.
Note that the TXNW signal can also be used to
trigger an event on the LOS pin. This is done by
setting the TXER bit in the Interrupt Control Register
(INTC).
TRANSMITTER OPERATION
The transmitter accepts either NRZ coded data or
positive and negative AMI signals and generates
current pulses on the LOUTP and LOUTN pins.
When properly connected to a 1:2CT center-tapped
transformer, an AMI pulse is generated which can
drive a 75Ω coaxial cable.
When the recommended transformer is used and
when DS3 mode is selected, the transmitted pulse
shape at the end of the 75Ω terminated cable of 0 to
450 feet will fit the DS3 template in ANSI T1.102-
1993 and Telcordia GR-499-CORE standard
documents. For STS-1 applications, the transmitted
pulse for a short cable meets the requirements of
Telcordia GR-253-CORE. For E3 applications, the
transmitted pulse for a short cable meets the
requirements of ITU-T G.703.
JITTER ATTENUATOR
Jitter Attenuation function is provided on-chip. The
Jitter Attenuator can be configured to be in the
transmit or the receive path. When configured in the
transmit path, the input clock at TCLK pin is passed
through a very low bandwidth digital PLL. The
corresponding transmit data is buffered into a FIFO
and clocked out using the de-jittered output clock of
the PLL. When configured in the receive path, the
recovered clock is passed through the low
bandwidth digital PLL, and the corresponding
receive data is buffered into the FIFO and clocked
out using the de-jittered clock.
The Jitter Attenuator can be configured by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
LINE BUILD-OUT
JAEN
bit
JASL
bit
X
The Line Build-Out (LBO) function controls the
transmit amplitude and pulse shape in DS3 and
STS-1 modes. The selection of LBO depends on
the amount of cable the transmitter is connected to.
When less than 225 ft of cable is used, the LBO pin
(or LBO bit) should be high. When 225ft or more
cable is used, the LBO pin (or LBO bit) should be
low.
Jitter Attenuator Mode
0
Jitter Attenuator disabled
Jitter Attenuator configured
to be in the receive path
Jitter Attenuator configured
to be in the transmit path
1
0
1
1
LBO settings can be controlled either from pins or
from register settings, depending on the status of
the Register Control bit, REGEN. Note that LBO
settings are ignored when in E3 mode.
TRANSMIT ENABLE
The TXEN pin controls the transmitter output. When
low, the transmitter output is disabled. Alternately,
the TXEN bit in the Mode Control register can
control the transmitter if the Register Control bit is
enabled.
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