78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the LOS pin to be activated. User may set as many bits as
required.
DFLT
BIT
NAME
TYPE
DESCRIPTION
Interrupt Pin Polarity Selection:
VALUE
7
INPOL
R/W
0
0 : Interrupt output is active-low
1 : Interrupt output is active-high
6:4
3
RSVD
R/O
R/W
X
0
Reserved
Reserved for test only. Must be set to ‘0’.
Jitter Attenuator Error Event:
JAFLG
2
1
0
JAER
RXER
TXER
R/W
R/W
R/W
0
1
0
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
- 9 -
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
