78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
The jitter tolerance of 78P2341JAT meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824, GR-499 (Cat I and II)
for DS3 rates; and the requirements of GR-253 for
STS1 rates.
When the Jitter Attenuator is disabled, the jitter
transfer function meets the requirements of GR-499
for Category II DS3 interfaces.
FUNCTIONAL DESCRIPTION
The 78P2341JAT contains all the necessary
transmit and receive circuitry for connection
between E3, DS3, or STS-1 interfaces and
Framer/Mapper ICs.
OPERATING RATE
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below. The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
When the Jitter Attenuator is enabled, the
78P2341JAT meets the requirements of GR-499
and GR-253 for all categories of DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates.
standards,
To check conformance with other
please
refer
to
the
JITTER
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
REFERENCE CLOCK
Standard
MSL0 pin
DS3 bit
E3 bit
The clock recovery system employs a digital PLL,
which uses a line-rate reference clock frequency.
This reference frequency can be input to the CKREF
pin or it can utilize the transmitter clock input TCLK
when CKREF is left floating or pulled high.
E3
L
H
Z
Z
0
1
0
1
1
0
0
1
DS3
STS-1
STS-1
RECEIVER OPERATION
RECEIVER MONITOR MODE
The receiver inputs LINP and LINN are either
When the MON pin is high, 20dB of flat gain is
applied to the incoming signal before it is fed to the
receive equalizer. Alternately, the MON bit in the
Mode Control Register can be used if the Register
Control bit, REGEN, is enabled.
transformer-coupled or capacitor-coupled to the line
signal.
In applications where the highest
performance and isolation are required, a 1:1
transformer is used in the receive path. In
applications where isolation is provided elsewhere in
the circuit, capacitor coupling can be used. The
receiver inputs should be line terminated externally
with a termination resistor.
SIGNAL DETECT
When the received signal is below a minimum
threshold, the LOS signal (bit) in the Status Monitor
register is asserted. A time delay is provided before
this output is active so that transient interruptions do
not cause false indications. By default, the LOS
signal is also used to trigger an interrupt on the LOS
pin. Note that the error events that control the
assertion of the LOS pin can be configured in the
Interrupt Control Register (INTC).
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss. When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer. The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths. Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
Note: In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection. If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.
to maintain
a
constant voltage level output
regardless of the input voltage level.
- 2 -
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
