78P2241B
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: (The 28-pin PLCC is compatible with 78P7200)
NAME
PIN
TQFP
42
44
33
PIN
PLCC
1
3
23
TYPE DESCRIPTION
LIN+
LIN-
RCLK
I
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
Receive Clock: Recovered receive clock.
O
O
RPOS/
RNRZ
35
25
Receive Positive Data / NRZ Data: When ENDEC is high, this
pin indicates reception of a positive AMI pulse on the coax
cable. When ENDEC is low, it outputs NRZ data.
RNEG/
LCV
34
24
O
O
Receive Negative Data/LCV: When ENDEC is high, this pin
indicates reception of a negative AMI pulse on the coax. When
ENDEC is low this pin indicates the occurrence of a line
code violation.
Loss of Signal: logic low indicates that receiver signal (LIN±)
is below the threshold level for 175±75 periods. RPOS and
RNEG are forced low when LOS=0.
39
27
LOS
LOUT+
LOUT-
TCLK
9
11
18
9
11
16
O
I
Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301Ω resistor.
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P2241.
TPOS/
TNRZ
16
17
14
15
I
Transmit Positive Data / Transmit NRZ: When ENDEC is
high, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time
that TNEG is high.
When ENDEC is low, NRZ data received on this pin is encoded
into positive and negative AMI pulses.
TNEG
I
Transmit Negative Data: When ENDEC is high, a logic one on
this pin generates a negative AMI pulse on the coax. This pin
should not be high at the same time that TPOS/TNRZ is high.
When ENDEC is low, this pin is ignored.
LBO
13
15
12
13
I
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used with
less than 225ft of cable.
I3
E#
DS3, E3 and STS-1 Select: Set low for E# applications. Set
high for DS3, allow to float for STS-1 operation. Formerly
OPT! On the 78P7200.
TXEN
MON
ICKP
22
28
10
18
21
10
I
I
Transmitter Enable: When high, enables transmitter. When
low, tri-states transmitter drivers, LOUT±. This pin was
called OPT@ on 78P7200.
DSX3 / E3 Monitor Select: When set high, an additional 20-
dB gain stage is added to the receiver gain. This pin was
tied to GND on the 78P7200.
Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set high,
the polarity of TCLK is inverted. When allowed to float, the
polarities of both RCLK and TCLK are inverted.
Loop-back Select: When high, neither loop-back is activated.
When allowed to float RPOS, RNEG and RCLK are looped
back onto TPOS, TNEG and TCLK. When low, LOUT± is
looped back onto LIN±.
I3
40
28
I3
P
LPBK
VCC
5,6,20,
7,17,26
Power Supply.
21,37,38
Page: 4 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
