78P2241B
E3/DS3/STS-1
Transceiver
The AMI signal first enters a selectable fixed 20 dB
amplifier stage that compensates for very low
amplitude DSX3 monitor signal when MON pin is
held high. The signal then enters an equalizer and
AGC gain stage. The equalizer is designed to
overcome intersymbol interference caused by long
cable lengths. Because the equalizer is adaptive,
the circuit will work with all square shaped signals
such as DS3 high or 34 Mbit/s E3. The variable gain
differential amplifier maintains a constant voltage
level output regardless of the input voltage level.
The gain of the amplifier is adjusted by detecting the
peak of the signal and comparing it to a fixed
reference.
FUNCTIONAL DESCRIPTION
The 78P2241B is a single chip line interface IC
designed to work with a 51.84 Mbit/s STS-1, 44.736
Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver
recovers clock, positive data and negative data from
an Alternate Mark Inversion (AMI) signal. The AMI
line input signal should be B3ZS or HDB3 coded.
The transmitter accepts clock, positive, and negative
data and converts them into an AMI signal to drive a
75
Ω coaxial cable. The shape of the transmitted
signal though any cable length of 0 to 450 feet
complies with the published templates of ANSI
T1.102-1993, Telcordia TR-NWT-000499 and GR-
253-CORE, ITU-T G.703. The 78P2241B is designed
to work with B3ZS or HDB3 coded signals. The
B3ZS or HDB3 encoding and decoding functions are
normally included in the framer ICs; however, a
selectable B3ZS/HDB3 ENDEC is included in the
78P2241B for interface to binary NRZ data. The
78P2241B is designed to easily connect to popular
ATM framer ICs such as PMC 7345 (SUNI-PDH),
PMC 7346 (QJET) and 7321.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a phase locked loop with an
auxiliary frequency-sensitive acquisition loop. This
system permits the loop to independently lock to the
frequency and phase of the incoming data stream
without the need for an external, high precision
tuned circuits or reference clock signal.
The jitter tolerance of the 78P2241B meets the
requirements of Telcordia GR-499-CORE for
Category I equipment for DS3 rates and exceeds the
requirements of ITU-T G.823 for E3 rates.
OPERATION SPEED
Internal bias generators that are adjusted by the
value of the RFO set the 78P2241B PLL center
frequency and Transmitter amplitude for the different
standards. The E# pin controls the equalizer
response and the transmitter pulse shape and
amplitude. The following table shows the proper
settings.
Pin 21
MON
Receive
Range
mVpk
Mode
Low
High
Low
High
90-850
25-80
104-1200
25-80
DS3/STS-1 normal
DS3 monitor
E3 normal
Standard
E3
RFO Value, k
6.81
Ω
E# pin setting
Low
E3 monitor
DS3
5.23
High
STS-1
4.53
Float
B3ZS/HDB3 DECODER
RECEIVER
The 78P2241B includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). When the ENDEC pin
is low, the ENDEC is selected and the receiver
generates a composite NRZ logic data following the
B3ZS (for DS3/STS-1) or HDB3 (for E3) substitution
codes via the RPOS/RNRZ pin as shown below.
The receiver input can be either transformer-coupled
or capacitor coupled to the AMI signal. In
applications where the highest performance and
isolation is required, a 1:1 transformer is used on the
receiver path. In the applications, where isolation is
provided elsewhere in the circuit, an AC coupling can
be used.
The inputs to the IC are internally
Pin 20
ENDEC RPOS/RNRZ
High
Low
referenced to Vcc. Since the input impedance of the
78P2241B is high, the AMI line must be terminated to
RNEG
Negative AMI
No Connect
Positive AMI
NRZ data
75
Ω
.
The input signal of the 78P2241B must be
limited to a maximum of three consecutive zeros
using a coding scheme such as B3ZS or HDB3.
Page: 2 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
