73S8014R Data Sheet
DS_8014R_012
Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014R 20-Pin SOP Pin Definitions
Pin
Number
Equivalent
Circuit
Pin Name
Type
Description
Card Interface
Card I/O: Data signal to/from card. Includes an 11k pull-up
resistor to VCC.
I/O
14
15
IO
O
Figure 14
RST
Figure 13 Card reset: provides reset (RST) signal to card.
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or frequency
of the external clock signal applied on XTALIN and CLKDIV
selections.
CLK
17
19
O
I
Figure 12
Card Presence switch: active high indicates card is present.
Figure 16
PRES
Includes a high-impedance pull-down current source.
Card power supply – logically controlled by sequencer, output of
Figure 11 LDO regulator. Requires an external filter capacitor to the card
GND.
VCC
GND
18
16
PSO
GND
–
Card ground.
Host Processor Interface
Command VCC (negative assertion): Logic low on this pin causes
CMDVCC
6
7
I
I
Figure 16 the LDO regulator to ramp the VCC supply to the card and initiates
a card activation sequence, if a card is present.
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and
card interface, logic low selects 3 volt operation. When the part is
to be used with a single card voltage, this pin should be tied to
either GND or VDD. However, it includes a high impedance pull-up
5V/#V
Figure 16
resistor to default this pin high (selection of 5V card) when not
connected. This pin shall not be changed when CMDVCC is low.
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1
CLKDIV2
20
5
CLKDIV1
CLKDIV2
CLOCK RATE
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
I
Figure 16
0
0
1
1
0
1
1
0
Interrupt signal to the processor. Active Low - Multi-function
OFF
1
O
Figure 10 indicating fault conditions and card presence. Open drain output
configuration – It includes an internal 20kΩ pull-up to VDD.
RSTIN
I/OUC
2
3
I
Figure 16 Reset Input: This signal is the reset command to the card.
System controller data I/O to/from the card. Includes an 11K
IO
Figure 15
pull-up resistor to VDD.
6
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
