73S8014R Data Sheet
DS_8014R_012
Figures
Figure 1: 73S8014R Block Diagram.......................................................................................................................... 2
Figure 2: 73S8014R 20-SOP Pin Out........................................................................................................................ 5
Figure 3: 73S8014R – Typical Application Schematic ............................................................................................ 15
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low ............................................................. 18
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low............................................................. 19
Figure 6: Deactivation Sequence ............................................................................................................................ 19
Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20
Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21
Figure 9: I/O – I/OUC Delays – Timing Diagram..................................................................................................... 21
Figure 10: Open Drain type – OFF.......................................................................................................................... 22
Figure 11: Power Input/Output Circuit, VDD, VPC, VCC ........................................................................................ 22
Figure 12: Smart Card CLK Driver Circuit ............................................................................................................... 23
Figure 13: Smart Card RST Driver Circuit............................................................................................................... 23
Figure 14: Smart Card IO Interface Circuit.............................................................................................................. 24
Figure 15: Smart Card IOUC Interface Circuit......................................................................................................... 24
Figure 16: General Input Circuit .............................................................................................................................. 25
Figure 17: Oscillator Circuit ..................................................................................................................................... 25
Figure 18: VDDF_ADJ............................................................................................................................................. 26
Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27
Tables
Table 1: 73S8014R 20-Pin SOP Pin Definitions ....................................................................................................... 6
Table 2: Absolute Maximum Device Ratings............................................................................................................. 8
Table 3: Recommended Operating Conditions ......................................................................................................... 8
Table 4: Package Thermal Parameters..................................................................................................................... 9
Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9
Table 6: Digital Signals Characteristics................................................................................................................... 11
Table 7: DC Characteristics..................................................................................................................................... 12
Table 8: Voltage Fault Detection Circuits................................................................................................................ 13
Table 9: Order Numbers and Packaging Marks...................................................................................................... 28
4
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
