73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
CONTROL REGISTER 0
D7
D6
D5
D4
D3
D2
D1
D0
CR0
000
MODUL. MODUL.
OPTION
MODUL.
TYPE 0
TRANSMIT
MODE 2
TRANSMIT
MODE 1
TRANSMIT
MODE 0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
TYPE 1
BIT NO.
NAME
CONDITION
DESCRIPTION
D0
Answer/
Originate
0
Selects answer mode (transmit in high band, receive in low
band).
1
Selects originate mode (transmit in low band, receive in
high band).
D1
Transmit
Enable
0
1
Disables transmit output at TXA.
Enables transmit output at TXA.
Note: Transmit Enable must be set to 1 to allow activation
of Answer Tone or DTMF.
D5 D4 D3 D2
Selects power down mode. All functions disabled except
digital interface.
0
0
0
0
0
0
0
1
Internal synchronous mode. In this mode TXCLK is an
internally derived 600,1200 or 2400 Hz signal. Serial input
data appearing at TXD must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXD on the falling
edge of RXCLK.
D5, D4,
D3, D2
Transmit
Mode
0
0
0
0
1
1
0
1
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to
EXCLK pin, and a 600, 1200 or 2400 Hz clock must be
supplied externally.
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to the
RXCLK pin in this mode.
0
0
0
0
1
1
1
1
1
X
0
0
1
1
0
0
1
0
1
0
Selects asynchronous mode - 8 bits/character (1 start bit, 6
data bits, 1 stop bit).
Selects asynchronous mode - 9 bits/character (1 start bit, 7
data bits, 1 stop bit).
Selects asynchronous mode - 10 bits/character (1 start bit,
8 data bits, 1 stop bit).
Selects asynchronous mode - 11 bits/character (1 start bit,
8 data bits, Parity and/or 1 or 2 stop bits).
Selects FSK operation.
D6 D5
D6,D5
Modulation
Type
QAM
DPSK
FSK
1
0
0
0
0
1
Page: 8 of 31
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
