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73K224L 参数 Datasheet PDF下载

73K224L图片预览
型号: 73K224L
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器
文件页数/大小: 31 页 / 243 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73K224L  
V.22bis, V.22, V.21, Bell 212A, 103  
Single-Chip Modem  
DATA SHEET  
PIN DESCRIPTION  
POWER  
NAME  
GND  
VDD  
TYPE DESCRIPTION  
I
I
System Ground.  
Power supply input, 5V -5% +10%. Bypass with 0.22 µF and 22 µF capacitors to  
GND.  
VREF  
ISET  
O
I
An internally generated reference voltage. Bypass with 0.22 µF capacitor to  
GND.  
Chip current reference. Sets bias current for op-amps. The chip current is set by  
connecting this pin to VDD through a 2 MΩ resistor. Iset should be bypassed to  
GND with a 0.22 µF capacitor.  
PARALLEL MICROPROCESSOR INTERFACE  
ALE  
I
Address latch enable. The falling edge of ALE latches the address on AD0-AD2  
and the chip select on CS.  
AD0- AD7  
CS  
I/O  
Address/data bus. These bidirectional tri-state multiplexed lines carry inform-  
ation to and from the internal registers.  
/Tristate  
I
Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0-  
AD7 will not be driven and no registers will be written if CS (latched) is not active.  
CS is latched on the falling edge of ALE.  
CLK  
O
Output clock. This pin is selectable under processor control to be either the  
crystal frequency (for use as a processor clock) or 16 x the data rate for use as a  
baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal  
frequency on reset.  
INT  
O
Interrupt. This open drain /weak pull-up, output signal is used to inform the  
processor that a detect flag has occurred. The processor must then read the  
detect register to determine which detect triggered the interrupt. INT will stay  
active until the processor reads the detect register or does a full reset.  
RD  
I
I
Read. A low requests a read of the 73K224L internal registers. Data cannot be  
output unless both RD and the latched CS are active or low.  
RESET  
Reset. An active high signal on this pin will put the chip into an inactive state. All  
control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the  
CLK pin will be set to the crystal frequency. An internal pull down resistor permits  
power on reset using a capacitor to VDD.  
WR  
I
Write. A low on this informs the 73K224L that data is available on AD0-AD7 for  
writing into an internal register. Data is latched on the rising edge of WR. No data  
is written unless both WR and the latched CS are active (low).  
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes  
DATA and AD0, AD1 and AD2 become the address only.  
Page: 4 of 31  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1