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73K224L 参数 Datasheet PDF下载

73K224L图片预览
型号: 73K224L
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器
文件页数/大小: 31 页 / 243 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73K224L  
V.22bis, V.22, V.21, Bell 212A, 103  
Single-Chip Modem  
DATA SHEET  
CONTROL REGISTER 0 (continued)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
CR0  
000  
MODUL. MODUL.  
OPTION  
MODUL.  
TYPE 0  
TRANSMIT  
MODE 2  
TRANSMIT  
MODE 1  
TRANSMIT  
MODE 0  
TRANSMIT  
ENABLE  
ANSWER/  
ORIGINATE  
TYPE 1  
BIT NO.  
NAME  
CONDITION  
DESCRIPTION  
D7  
Modulation  
Option  
0
QAM selects 2400 bit/s. DPSK selects 1200 bit/s.  
FSK selects 103 mode.  
1
DPSK selects 600 bit/s.  
FSK selects V.21 mode.  
CONTROL REGISTER 1  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
TRANSMIT  
PATTERN  
1
TRANSMIT  
PATTERN  
0
ENABLE  
DETECT  
INT.  
BYPASS  
SCRAMB  
CLK  
CONTROL  
RESET  
TEST  
MODE 1  
TEST  
MODE 0  
CR1  
001  
BIT NO.  
NAME  
CONDITION  
DESCRIPTION  
D1 D0  
D1, D0  
Test Mode  
Selects normal operating mode.  
0
0
0
1
Analog loopback mode. Loops the transmitted analog  
signal back to the receiver, and causes the receiver to use  
the same carrier frequency as the transmitter. To squelch  
the TXA pin, TRANSMIT ENABLE bit as well as Tone Reg  
bit D2 must be low.  
1
1
0
1
Selects remote digital loopback. Received data is looped  
back to transmit data internally, and RXD is forced to a  
mark. Data on TXD is ignored.  
Selects local digital loopback. Internally loops TXD back to  
RXD and continues to transmit data carrier at TXA pin.  
D2  
D3  
Reset  
0
1
Selects normal operation.  
Resets modem to power down state. All control register bits  
(CR0, CR1, CR2, CR3 and Tone) are reset to zero except  
CR3 bit D2. The output of the clock pin will be set to the  
crystal frequency.  
Clock Control  
0
1
Selects 11.0592 MHz crystal echo output at CLK pin.  
Selects 16 X the data rate, output at CLK pin in DPSK/QAM  
modes only.  
Page: 9 of 31  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1