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73K224BL 参数 Datasheet PDF下载

73K224BL图片预览
型号: 73K224BL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器瓦特/集成混合 [Single-Chip Modem w/ Integrated Hybrid]
分类和应用: 调制解调器
文件页数/大小: 33 页 / 202 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73K224BL  
V.22bis, V.22, V.21, Bell 212A, 103  
Single-Chip Modem w/ Integrated Hybrid  
DATA SHEET  
PARALLEL MICROPROCESSOR INTERFACE (continued)  
NAME  
PIN  
TYPE  
DESCRIPTION  
WR  
14  
I
WRITE: A low on this informs the 73K224BL that data is available  
on AD0-AD7 for writing into an internal register. Data is latched  
on the rising edge of WR. No data is written unless both WR and  
the latched CS are low.  
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE  
NAME  
PIN  
TYPE  
DESCRIPTION  
AD0-AD2  
5-7  
I
REGISTER ADDRESS SELECTION: These lines carry register  
addresses and should be valid during any read or write  
operation.  
DATA (AD7)  
12  
15  
I/O  
I
SERIAL CONTROL DATA: Data for a read/write operation is  
clocked in or out on the falling edge of the EXCLK pin. The  
direction of data flow is controlled by the RD pin. RD low outputs  
data. RD high inputs data.  
RD  
READ: A low on this input informs the 73K224BL that data or  
status information is being read by the processor. The falling  
edge of the RD signal will initiate a read from the addressed  
register. The RD signal must continue for eight falling edges of  
EXCLK in order to read all eight bits of the referenced register.  
Read data is provided LSB first. Data will not be output unless  
the RD signal is active.  
WR  
14  
I
WRITE: A low on this input informs the 73K224BL that data or  
status information has been shifted in through the DATA pin and  
is available for writing to an internal register. The normal  
procedure for a write is to shift in data LSB first on the DATA pin  
for eight consecutive falling edges of EXCLK and then to pulse  
WR low. Data is written on the rising edge of WR.  
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes  
DATA and AD0, AD1 and AD2 become the register address.  
Page: 6 of 33  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1