73K224BL
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
PIN DESCRIPTION
POWER
NAME
GND
VDD
PIN
1
TYPE
DESCRIPTION
I
I
System ground
16
Power supply input, 5 V ±10% (73K224BL). Bypass with 0.1 and
22 µF capacitors to GND.
VREF
ISET
31
28
O
I
An internally generated reference voltage. Bypass with 0.1 µF
capacitor to ground.
Chip current reference. Sets bias current for op-amps. The chip
current is set by connecting this pin to VDD through a
2 MΩ resistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
13
5-12
23
I
I/O
I
ADDRESS LATCH ENABLE: The falling edge of ALE latches the
address on AD0-AD2 and the chip select on CS.
AD0-AD7
CS
ADDRESS/DATA BUS: These bi-directional tri-state multiplexed
lines carry information to and from the internal registers.
CHIP SELECT: A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. AD0-AD7 will not be
driven and no registers will be written if CS (latched) is not active.
The state of CS is latched on the falling edge of ALE.
CLK
2
O
O
OUTPUT CLOCK: This pin is selectable under processor control
to be either the crystal frequency (for use as a processor clock) or
16 times the data rate for use as a baud rate clock in DPSK
modes only. The pin defaults to the crystal frequency on reset.
INT
20
INTERRUPT: This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor must
then read the Detect Register to determine which detect triggered
the interrupt. INT will stay low until the processor reads the detect
register or does a full reset.
RD
15
30
I
I
READ: A low requests a read of the 73K224BL internal registers.
Data can not be output unless both RD and the latched CS are
active or low.
RESET
RESET: An active high signal on this pin will put the chip into an
inactive state. All Control Register bits (CR0, CR1, tone) will be
reset. The output of the CLK pin will be set to the crystal
frequency. An internal pull-down resistor permits power-on-reset
using a capacitor to VDD.
Page: 5 of 33
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
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