73K224BL
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
Hz (answer, mark and space). Demodulation involves
detecting the received frequencies and decoding them
into the appropriate binary value. The rate converter
The synch/asynch converter also has an extended
overspeed mode, which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at 7/8
rising edge of TXCLK the normal width.
and
scrambler/descrambler
are
automatically
bypassed in the FSK modes.
Both the synch/asynch rate converter and the data
descrambler are automatically bypassed in the
FSK modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering
corresponds to a 75% square root of raised Cosine
frequency response characteristic.
SYNCHRONOUS MODE
Synchronous operation is possible only in the
QAM or DPSK modes. Operation is similar to that
of the asynchronous mode except that data must
be synchronized to a provided clock and no
variation in data transfer rate is allowable. Serial
input data appearing at TXD must be valid on the
rising edge of TXCLK.
ASYNCHRONOUS MODE
TXCLK is an internally derived 1200 or 2400 Hz
signal in internal mode and is connected internally
to the RXCLK pin in slave mode. Receive data at
the RXD pin is clocked out on the falling edge of
RXCLK. The asynch/synch converter is bypassed
when synchronous mode is selected and data is
transmitted at the same rate as it is input.
The asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 bit/s +1%, -2.5% even though the
modem’s output is limited to the nominal bit rate ±.01%
in DPSK and QAM modes. When transmitting in this
mode the serial data on the TXD input is passed
through a rate converter which inserts or deletes stop
bits in the serial bit stream in order to output a signal
that is the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog
modulator where quad-bit/di-bit encoding results in the
output signal. Both the rate converter and scrambler
can be bypassed for handshaking, and synchronous
operation as selected. Received data is processed in a
similar fashion except that the rate converter now acts
to reinsert any deleted stop bits and output data to the
terminal at no greater than the bit rate plus 1%. An
incoming break signal (low through two characters) will
be passed through without incorrectly inserting a stop
bit.
PARALLEL BUS CONTROL INTERFACE MODE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2
multiplexed address lines (latched by ALE) and
appear to a control microprocessor as seven
consecutive memory locations. Six control
registers are read/write memory. The detect and
ID registers are read only and cannot be modified
except by modem response to monitored
parameters.
Page: 3 of 33
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
