73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
PIN DESCRIPTION
POWER
NAME
GND
VDD
28-PIN
TYPE
DESCRIPTION
System Ground.
28
15
I
I
Power supply input, 5V ±10%. Bypass with 0.1 and 22 µF capacitors to
GND.
VREF
ISET
26
24
O
I
An internally generated reference voltage. Bypass with 0.1 µF
capacitor to ground.
Chip current reference. Sets bias current for op-amps. The chip
current is set by connecting this pin to VDD through a 2 MΩ resistor.
ISET should be bypassed to GND with a 0.1 µF capacitor.
PARALLEL MICROPROCESSOR INTERFACE
ALE
12
4-11
20
I
I/O
I
Address latch enable. The falling edge of ALE latches the address on
AD0-AD2 and the chip select on CS.
AD0-AD7
CS
Address/data bus. These bidirectional tri-state multiplexed lines carry
information to and from the internal registers.
Chip select. A low on this pin during the falling edge of ALE allows a
read cycle or a write cycle to occur. AD0-AD7 will not be driven and no
registers will be written if CS (latched) is not active. The state of CS is
latched on the falling edge of ALE.
CLK
1
O
O
Output clock. This pin is selectable under processor control to be either
the crystal frequency (for use as a processor clock) or 16 x the data
rate for use as a baud rate clock in DPSK modes only. The pin defaults
to the crystal frequency on reset.
Interrupt. This open drain output signal is used to inform the processor
that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INT
will stay low until the processor reads the detect register or does a full
reset.
INT
17
RD
14
25
I
I
Read. A low requests a read of the 73K222AL internal registers. Data
cannot be output unless both RD and the latched CS are active or low.
RESET
Reset. An active high signal on this pin will put the chip into an inactive
state. All control register bits (CR0, CR1, Tone) will be reset. The
output of the CLK pin will be set to the crystal frequency. An internal
pull down resistor permits power on reset using a capacitor to VDD.
Page: 4 of 27
© 2007 TERIDIAN Semiconductor Corporation
Rev 6.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
