Data Sheet 71M6531D/F-71M6532D/F
Table 17: The S0CON (UART0) Register (SFR 0x98)
FDS 6531/6532 005
Bit
Symbol
SM0
Function
S0CON[7]
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
N/A
SM0
SM1
0
1
2
3
0
0
1
1
0
1
0
1
8-bit UART
9-bit UART
9-bit UART
S0CON[6]
SM1
S0CON[5]
S0CON[4]
S0CON[3]
SM20
REN0
TB80
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
S0CON[2]
RB80
Transmit interrupt flag; set by hardware after completion of a serial trans-
fer. Must be cleared by software.
S0CON[1]
S0CON[0]
TI0
RI0
Receive interrupt flag; set by hardware after completion of a serial recep-
tion. Must be cleared by software.
Table 18: The S1CON (UART1) register (SFR 0x9B)
Bit
Symbol
Function
Sets the baud rate and mode for UART1.
S1CON[7]
SM
SM
0
Mode
Description
9-bit UART
8-bit UART
Baud Rate
variable
variable
A
B
1
S1CON[5]
S1CON[4]
S1CON[3]
SM21
REN1
TB81
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU, de-
pending on the function it performs (parity check, multiprocessor commu-
nication etc.)
S1CON[2]
S1CON[1]
S1CON[0]
RB81
TI1
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial trans-
fer. Must be cleared by software.
RI1
Receive interrupt flag, set by hardware after completion of a serial recep-
tion. Must be cleared by software.
Table 19: PCON Register Bit Description (SFR 0x87)
Bit
Symbol
Function
The SMOD bit doubles the baud rate when set
Not used.
PCON[7]
PCON[6:2]
SMOD
–
Stops MPU flash access and MPU peripherals including timers and
UARTs when set until an external interrupt is received.
PCON[1]
PCON[0]
STOP
IDLE
Stops MPU flash access when set until an internal interrupt is received.
28
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
