FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt ser-
vice is terminated by a return from instruction, RETI. When an RETI is performed, the processor will re-
turn to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the in-
terrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the fol-
lowing conditions are met:
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26.
The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).
The interrupt request register, IRCON (see Table 29).
The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol
EAL
WDT
–
Function
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1.
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0.
ET1
EX1
ET0
EX0
Table 25: The IEN1 Bit Functions (SFR 0xB8)
Bit
Symbol
Function
–
IEN1[7]
Not used.
–
IEN1[6]
Not used.
IEN1[5]
IEN1[4]
IEN1[3]
IEN1[2]
IEN1[1]
IEN1[0]
EX6
EX5
EX4
EX3
EX2
–
EX6 = 0 disables external interrupt 6.
EX5 = 0 disables external interrupt 5.
EX4 = 0 disables external interrupt 4.
EX3 = 0 disables external interrupt 3.
EX2 = 0 disables external interrupt 2.
Not Used.
Table 26: The IEN2 Bit Functions (SFR 0x9A)
Bit
Symbol
Function
IEN2[0]
ES1
ES1 = 0 disables the serial channel 1 interrupt.
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