FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Table 13: Stretch Memory Cycle Width
Read signal width
Write signal width
Stretch
Value
CKCON[2:0]
memaddr
memrd
memaddr
memwr
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
Table 14 shows the location and description of the SFRs specific to the 71M6531D/F and 71M6532D/F.
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs
Register
SFR
Address
Bit Field
Name
R/W
Description
(Alternate
Name)
EEDATA
0x9E
0x9F
R/W I2C EEPROM interface data register.
EECTRL
R/W I2C EEPROM interface control register. See
Section 1.5.14 EEPROM Interface for a descrip-
tion of the command and status bits available
for EECTRL.
ERASE
(FLSH_ERASE)
0x94
W
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the Flash Memory section for details.
FL_BANK
0xB6[2:0]
0xB7
R/W Flash Bank Selection.
PGADDR
(FLSH_PGADR)
R/W Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
FLSHCRL
0xB2[0]
0xB2[1]
FLSH_PWE
R/W Program Write Enable:
0: MOVX commands refer to XRAM Space,
normal operation (default).
1: MOVX @DPTR,A moves A to Program
Space (Flash) @ DPTR.
FLSH_MEEN
W
Mass Erase Enable:
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Must be re-written for each new Mass Erase
cycle.
0xB2[6]
0xB2[7]
SECURE
R/W Enables security provisions that prevent exter-
nal reading of flash memory and CE program
RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
PREBOOT
R
Indicates that the preboot sequence is active.
v1.2
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