Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 7 shows the address, type, use and size of the various memory components.
Only the memory ranges shown in Table 7 contain physical memory.
Table 7: Memory Map
Address
(hex)
Memory
Technology
Memory
Type
Memory Size
(bytes)
Name
Typical Usage
00000-1FFFF/ Flash Memo- Non-volatile
00000-3FFFF ry
Program memory
MPU Program and
non-volatile data
128 KB/
256 KB
on 1K boun- Flash Memo- Non-volatile
Program memory
CE program
8 KB max.
4 KB
256
dary
ry
0000-0FFF
Static RAM
Volatile
Volatile
External RAM
(XRAM)
Shared by CE and
MPU
2000-20BF,
20C8-20FF
Static RAM
Configuration RAM, Hardware control
I/O RAM
20C0-20C7
Static RAM Non-volatile Configuration RAM,
Battery-buffered
memory
8
(battery)
I/O RAM
0000-00FF
Static RAM
Volatile
Internal RAM
Part of 80515 Core
256
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire 64 KB of external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0]), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is selected
when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data poin-
ters are not affected by the LSB of the DPS register. All DPTR related instructions use the currently se-
lected DPTR for any activity.
The second data pointer may not be supported by certain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions fast-
er compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save
and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
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