Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
1.3.1 Meter Equations
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various
meter equations. This assistance is controlled through I/O RAM location EQU (equation assist). The
Compute Engine (CE) firmware for residential configurations implements the equations listed in Table 5.
EQU specifies the equation to be used based on the number of phases used for metering.
Table 5: Meter Equations
Watt and VAR Formula
Element
Mux
Sequence
ALT Mux Se-
quence
EQU
Description
Element 0 Element 1
2
1 element, 2 W, 1φ with
neutral current sense
0
VA · IA
VA · IB
N/A
Sequence is
programmable programmable
Sequence is
with
SLOTn_SEL
with
SLOTn_ALTSEL
1 element, 3 W, 1φ
1
2
VA(IA-IB)/2
VA · IA
N/A
N/A
N/A
2 element, 3 W, 3φ Delta
VB · IB
1.3.2 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with RTM_E. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output enabled
by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See
Figure 20 for the RTM output format. RTM is low when not in use.
1.3.3 Pulse Generators
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and
YPULSE, as well as increased hardware support for the two original pulse generators (RPULSE and
WPULSE). The pulse generators can be used to output CE status indicators, SAG for example, to DIO
pins.
The polarity of the pulses may be inverted with PLS_INV. When this bit is set, the pulses are active high,
rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
The CE sign bit may be exported to the XPULSE and YPULSE pulse generator DFFs using the XPULSE
and YPULSE CE instructions. The DFF outputs are called XPULSE and YPULSE and may be brought
out on DIO8 and DIO9. Generally, the XPULSE and YPULSE DFF outputs are updated once on each
pass of the CE code, resulting in a maximum pulse frequency of 1260 Hz (assuming a multiplexer frame
is 13 CK32 cycles).
The YPULSE pin can be used by the CE code to generate interrupts based on sag events. This method
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section 4.3.6 CE Sta-
tus and Control for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE AND
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX
frame. The FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL[7:0] controls the delay to
the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles. If zero,
the FIFO is deactivated and the DFFs are updated immediately. Thus, NINTERVAL is 4*PLS_INTERVAL.
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs
5 updates per MUX interval and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/5/4 = 97.5. If PLS_INTERVAL = 98, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 97.
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