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SMS8198 参数 Datasheet PDF下载

SMS8198图片预览
型号: SMS8198
PDF下载: 下载PDF文件 查看货源
内容描述: 飞利浦TriMedia⑩处理器伴侣监控器的16K位2线串行存储器 [Philips TriMedia⑩ Processor Companion Supervisor With a 16K-bit 2-wire Serial Memory]
分类和应用: 存储监控
文件页数/大小: 14 页 / 79 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMS8198  
WRITE OPERATIONS  
While the internal write cycle is in progress, theSMS8198  
inputs are disabled, and the device will not respond to any  
The SMS8198 allows two types of write operations: byte requests from the master. Refer to Figure 6 for the  
write and page write. The byte write operation writes a address, ACKnowledge and data transfer sequence.  
single byte during the nonvolatile write period (tWR). The  
Page WRITE  
page write operation allows up to 16 bytes in the same  
The SMS8198 is capable of a 16-byte page write opera-  
page to be written during tWR  
.
tion. It is initiated in the same manner as the byte-write  
operation, but instead of terminating the write cycle after  
Byte WRITE  
After the slave address is sent (to identify the slave the first data word, the master can transmit up to 15 more  
device, specify high order word address and a read or words of data. After the receipt of each word, the  
write operation), a second byte is transmitted which SMS8198 will respond with an ACKnowledge.  
contains the low 8 bit addresses of any one of the 2,048  
The SMS8198 automatically increments the address for  
words in the array.  
subsequent data words. After the receipt of each word,  
Upon receipt of the word address, the SMS8198 re- the four low order address bits are internally incremented  
sponds with an ACKnowledge. After receiving the next byone. Thehighorderfivebitsoftheaddressbyteremain  
byteofdata,itagainrespondswithanACKnowledge.The constant. Should the master transmit more than sixteen  
master then terminates the transfer by generating a words, prior to generating the STOP condition, the ad-  
STOP condition, at which time the SMS8198 begins the dress counter will roll over,and the previously written  
internal write cycle.  
data will be overwritten. As with the byte-write operation,  
all inputs are disabled during the internal write cycle.  
Refer to Figure 6 for the address, ACKnowledge and data  
transfer sequence.  
If single byte-write only,  
Stop bit issued here.  
Acknowledges Transmitted from  
SMS8198 to Master Receiver  
Acknowledges Transmitted from  
SMS8198 to Master Receiver  
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SDA  
Bus  
A
10  
A
9
A
8
R
W
Word Address  
Data Byte n  
Data Byte n+1  
Data Byte n+15  
Activity  
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0  
0
S
T
O
P
S
T
A
R
T
Device  
Type  
Address  
A10,A9,A8  
Read/Write  
0= Write  
Slave Address  
Master Sends Read  
Request to Slave  
Master Writes Word  
Address to Slave  
Master Writes  
Data to Slave  
Master Writes  
Data to Slave  
Master Writes  
Data to Slave  
Master Transmitter  
to  
Master Transmitter  
to  
Master Transmitter  
to  
Master Transmitter  
to  
Master Transmitter  
to  
Slave Receiver  
Slave Receiver  
Slave Receiver  
Slave Receiver  
Slave Receiver  
Slave Transmitter  
to  
Slave Transmitter  
to  
Slave Transmitter  
to  
Slave Transmitter  
to  
Slave Transmitter  
to  
Master Receiver  
Master Receiver  
Master Receiver  
Master Receiver  
Master Receiver  
2036 ILL8.0  
Shading Denotes  
SMS8198  
SDA Output Active  
Figure 6. Page/Byte WRITE Mode  
2036 5.0 4/18/00  
7