S93WD462/S93WD463
SK
CS
DI
STANDBY
STATUS VERIFY
t
CS
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
2029 ILL 8.0
Figure 6. ERAL Instruction Timing
SK
CS
DI
STANDBY
STATUS VERIFY
t
CS
D
D
1
0
0
0
1
N
O
t
t
HZ
SV
DO
BUSY
READY
HIGH-Z
t
EW
2029 ILL 10.0
Figure 7. WRAL Instruction Timing
INSTRUCTION SET
Instruction
Start
Bit
Opcode
Address
x8
Data
x8
Comments
x16
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6–A0
A6–A0
x(A5–A0)
x(A5–A0)
x(A5–A0)
11xxxx
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
A6–A0
D7–D0
D7–D0
D15–D0
D15–D0
11xxxxx
00xxxxx
10xxxxx
01xxxxx
00xxxx
Write Disable
10xxxx
Clear All Addresses
WRAL
01xxxx
Write All Addresses
2029 PGM T5.0
2029-01 4/14/98
6