S93WD462/S93WD463
PIN CONFIGURATION
SOIC Package (S)
DIP Package (P)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
V
CS
SK
DI
V
CC
CC
SK
DI
RESET
RESET
GND
RESET
RESET
GND
DO
DO
2029 ILL1.0
PIN FUNCTIONS
will initiate a reset timeout after detecting a high to low
transition. Refer to the applications Information section
for more details on device operation as a debounce/
reset extender circuit.
Pin Name
CS
Function
Chip Select
SK
Clock Input
It should be noted the reset outputs are open drain.
When used as outputs driving a circuit they need to be
either tied high (RESET) or tied to ground (RESET)
through the use of pull-up or pull-down resistors. Refer
to the applications aid section for help in determining the
value of resistor to be used. Internally these pins are
weakly pulled up (RESET) and pulled down (RESET):
therefore, if the signals are not being used the pins may
be left unconnected.
DI
Serial Data Input
Serial Data Output
DO
VCC
+2.7 to 6.0V Power Supply
Ground
GND
RESET/RESET RESET I/O
DEVICE OPERATION
WATCHDOG TIMER DESCRIPTION
APPLICATIONS
The S93WD462/WD463 has a watchdog timer with a
nominal timeout period of 1.6 seconds. Whenever the
watchdogtimesout,itwillgeneratearesetoutputtoboth
pins 6 and 7. The watchdog timer is reset by any
transition on CS.
The S93WD462/WD463 is ideal for applications requir-
inglowvoltageandlowpowerconsumption. Thisdevice
provides microcontroller RESET control and can be
manually resettable.
The watchdog timer will be held in a reset state during
power-on while VCC is less than VTRIP. Once VCC
exceeds VTRIP the watchdog will continue to be held in
a reset state for the tPURST period. After tPURST it will be
releasedandthetimerwillbeginoperation.Ifeitherreset
input is asserted the watchdog timer will be reset and
remain in the reset condition until either tPURST has
expired or the reset input is released, whichever is
longer.
RESET CONTROLLER DESCRIPTION
The S93WD462/WD463 provides a precision reset con-
troller that ensures correct system operation during
brown-out and power-up/-down conditions. It is config-
ured with two open drain reset outputs; pin 7 is an active
high output and pin 6 is an active low output.
During power-up, the reset outputs remain active until
VCC reaches the VTRIP threshold. The outputs will con-
tinue to be driven for approximately 150 ms after reach-
ing VTRIP. The reset outputs will be valid so long as VCC
is ≥ 1.0V. During power-down, the reset outputs will
GENERAL OPERATION
TheS93WD462/WD463isa1024-bitnonvolatilememory
intended for use with industry standard microproces-
sors. The S93WD463 is organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. The S93WD462 is organized
as X8, seven 10-bit instructions control the reading,
writing and erase operations of the device. The device
operates on a single 3V or 5V supply and will generate
begin driving active when VCC falls below VTRIP
.
The reset pins are I/Os; therefore, the S93WD462/
WD463 can act as a signal conditioning circuit for an
externally applied reset. The inputs are edge triggered;
that is, the RESET input will initiate a reset timeout after
detecting a low to high transition and the RESET input
2029-01 4/14/98
2
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
