欢迎访问ic37.com |
会员登录 免费注册
发布采购

S24023SAT 参数 Datasheet PDF下载

S24023SAT图片预览
型号: S24023SAT
PDF下载: 下载PDF文件 查看货源
内容描述: 精密复位控制器和4K I2C存储器既RESET和RESET输出 [Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs]
分类和应用: 存储控制器
文件页数/大小: 14 页 / 157 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
 浏览型号S24023SAT的Datasheet PDF文件第3页浏览型号S24023SAT的Datasheet PDF文件第4页浏览型号S24023SAT的Datasheet PDF文件第5页浏览型号S24023SAT的Datasheet PDF文件第6页浏览型号S24023SAT的Datasheet PDF文件第8页浏览型号S24023SAT的Datasheet PDF文件第9页浏览型号S24023SAT的Datasheet PDF文件第10页浏览型号S24023SAT的Datasheet PDF文件第11页  
S24042/S24043  
Random Address Byte Read  
After the word address acknowledge is received by the  
Random address read operations allow the master to master, the master immediately reissues a start condition  
access any memory location in a random fashion. This followed by another slave address field with the R/W bit  
operation involves a two-step process. First, the master set to READ. The S24042/43 will respond with an ac-  
issues a write command which includes the start condi- knowledge and then transmit the 8-data bits stored at the  
tion and the slave address field (with the R/W bit set to addressed location. At this point, the master does not  
WRITE) followed by the address of the word it is to read. acknowledgethetransmissionbutdoesgeneratethestop  
This procedure sets the internal address counter of the condition. The S24042/43 discontinues data transmis-  
S24042/43 to the desired address.  
sion and reverts to its standby power mode. See Figure 8  
for the address, acknowledge and data transfer se-  
quence.  
A
C
K
A
C
K
A
C
K
A
8
R
W
R
W
X
X
Word Address  
X
X
X
Data Byte  
SDA Bus  
Activity  
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0  
0
1 0 1 0  
1
1
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Device  
Device  
Type  
Address  
Type  
Address  
Read/Write  
0= Write  
Read/Write  
1= Read  
Lack of ACK (low)  
from Master  
determines last  
data byte to be read  
Slave Address  
Slave Address  
Master sends Read  
request to Slave  
Master Writes Word  
Address to Slave  
Master Requests  
Data from Slave  
Slave sends  
Data to Master  
Master Transmitter  
to  
Master Transmitter  
to  
Master Transmitter  
to  
Slave Transmitter  
to  
Slave Receiver  
Slave Receiver  
Slave Receiver  
Master Receiver  
Slave Transmitter  
to  
Master Receiver  
Slave Transmitter  
to  
Master Receiver  
Slave Transmitter  
to  
Master Receiver  
Shading Denotes  
24042/43  
SDA Output Active  
2011 ILL11 1.0  
FIGURE 8. RANDOM ADDRESS BYTE READ MODE  
2011 2.1 8/2/00  
SUMMIT MICROELECTRONICS, Inc.  
7