S24042/S24043
SCL from
Master
1
9
8
Start
Condition
Data Output
from
tAA
Transmitter
Data Output
from
ACKnowledge
tAA
Receiver
2011 ILL6 1.0
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I2C BUS
General Description
The I2C bus was designed for two-way, two-line serial the master or the slave, will release the bus after transmit-
communicationbetweendifferentintegratedcircuits. The ting eight bits. During the ninth clock cycle, the receiver
two lines are: a serial data line (SDA), and a serial clock will pull the SDA line LOW to ACKnowledge that it re-
line (SCL). The SDA line must be connected to a positive ceived the eight bits of data (See Figure 3).
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
supply by a pull-up resistor, located somewhere on the
The S24042/43 will respond with an ACKnowledge after
bus (See Figure 1). Data transfer between devices may
recognition of a START condition and its slave address
be initiated with a START condition only when SCL and
byte. If both the device and a write operation are selected,
SDA are HIGH (bus is not busy).
the S24042/43 will respond with an ACKnowledge after
Input Data Protocol
the receipt of each subsequent 8-bit word.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 10.
In the READ mode, the S24042/43 transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24042/43 will continue to transmit data. If an
ACKnowledge is not detected, the S24042/43 will termi-
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is nate further data transmissions and awaits a STOP condi-
saidtobenotbusy.AHIGH-to-LOWtransitiononthedata tion before returning to the standby power mode.
line, while the clock is HIGH, is defined as the “START”
Device Addressing
condition. A LOW-to-HIGH transition on the data line,
Following a start condition the master must output the
while the clock is HIGH, is defined as the “STOP” condi-
address of the slave it is accessing. The most significant
tion (See Figure 2).
four bits of the slave address are the device type identifier
(see figure 4). For the S24042/43 this is fixed as 1010[B].
DEVICE OPERATION
The next two bits are don’t care. The next bit is the high
The S24042/43 is a 4,096-bit serial E2PROM. The device order address bit A8.
supports the I2C bidirectional data transmission protocol.
DEVICE
IDENTIFIER
The protocol defines any device that sends data onto the
DON’T CARE
busasa“transmitter”andanydevicewhich receivesdata
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the S24042/43 will be a “slave”
device, since it never initiates any data transfers.
A
8
X
X
R/W
1
0
1
0
2011 ILL7 1.1
FIGURE 4. SLAVE ADDRESS BYTE
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
