W150
Table 6. Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread On
Data Byte 0, Bit 3 = 1
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Spread Percentage
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.9ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
0.9ꢀ Center
0.5ꢀ Center
0.5ꢀ Center
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.3
124
150
140
105
110
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
115
120
100
133.3
112
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
103
66.8
83.3
75
124
Table 7. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Data Byte 0
Output Conditions
REF0:1,
CPU_F, 1:2 PCI_F, PCI0:5 IOAPIC0,_F
Function
Normal Operation
Test Mode
Bit 1
Bit 0
48 MHZ
24 MHZ
24 MHz
X1/4
0
0
1
1
0
1
0
1
Note 2
X1/2
Note 2
CPU/(2 or 3)
Note 2
14.318 MHz
X1
48 MHz
X1/2
Spread Spectrum
Tristate
Note 2
Hi-Z
14.318 MHz
Hi-Z
48 MHz
Hi-Z
24 MHz
Hi-Z
Hi-Z
Note:
2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
Rev 1.0,November 24, 2006
Page 8 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
