W150
Table 4. Byte Writing Sequence (continued)
Byte
Sequence Byte Name Bit Sequence
Byte Description
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to Table 5 The data bits in Data Bytes 0–5 set internal W150 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence is
11010010, as noted above. For description of bit control functions, refer to Table 5,
Data Byte Serial Configuration Map.
6
7
8
9
10
11
Don’t Care
Unused by the W150, therefore bit values are ignored (Don’t Care).
Writing Data Bytes
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–5 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
3
–
–
–
–
–
–
–
–
–
–
(Reserved)
–
–
0
0
0
0
0
SEL_2
See Table 6
See Table 6
See Table 6
SEL_1
SEL_0
Frequency Table Selection
Frequency
Controlled by FS
(3:0) Table 2
Frequency
Controlled by SEL
(3:0) Table 6
2
–
–
–
–
SEL3
Refer to Table 6
0
1–0
Bit 1
Bit 0
Function (See Table 7 for function details)
Normal Operation
(Reserved)
00
0
0
1
1
0
1
0
1
Spread Spectrum On
All Outputs Three-stated
Data Byte 1
7
6
5
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
–
–
–
–
3
2
1
0
46
49
51
52
SDRAM_F
CPU2
CPU1
CPU_F
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
Data Byte 2
7
6
–
8
–
(Reserved)
–
–
0
1
1
PCI_F
PCI5
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
5
16
Rev 1.0,November 24, 2006
Page 6 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
