W150
Table 5. Data Bytes 0–5 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
PCI4
Control Function
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
0
1
Default
4
3
2
1
0
14
13
12
11
9
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
1
1
1
1
1
PCI3
PCI2
PCI1
PCI0
Data Byte 3
7
6
–
–
–
(Reserved)
–
–
0
0
1
1
1
–
(Reserved)
–
–
5
4
3
29
30
48MHz
24MHz
Clock Output Disable
Clock Output Disable
Low
Low
Low
Active
Active
Active
33, 32, SDRAM12:15 Clock Output Disable
25, 24
2
1
0
22, 21,
19, 18
SDRAM8:11 Clock Output Disable
SDRAM4:7 Clock Output Disable
SDRAM0:3 Clock Output Disable
Low
Low
Low
Active
Active
Active
1
1
1
39, 38,
36, 35
44, 43,
41, 40
Data Byte 4
7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 5
7
6
–
–
–
(Reserved)
–
–
–
–
0
0
1
1
0
0
1
1
–
IOAPIC_F
IOAPICO
–
(Reserved)
5
4
3
2
1
0
54
55
–
Disabled
Low
Low
–
Active
Active
–
Disabled
(Reserved)
–
–
(Reserved)
–
–
2
REF1
REF0
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
3
Rev 1.0,November 24, 2006
Page 7 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
