W144
Data Byte 2
7
6
5
4
3
2
1
0
–
7
–
(Reserved)
–
–
0
1
0
1
1
1
1
1
PCI_F
–
Clock Output Disable
(Reserved)
Low
–
Active
–
–
13
12
11
10
8
PCI5
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Data Byte 3
7
6
5
4
3
–
–
–
–
(Reserved)
–
–
–
0
0
1
1
0
1
(Reserved)
–
26
25
–
48MHz
24MHz
–
Clock Output Disable
Clock Output Disable
(Reserved)
Low
Low
–
Active
Active
–
2
1
0
21, 20,
18, 17
SDRAM8:11 Clock Output Disable
Low
Active
32, 31,
29, 28
SDRAM4:7
SDRAM0:3
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
1
1
38, 37,
35, 34
Data Byte 4
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 5
7
6
5
4
3
2
1
0
–
–
–
(Reserved)
–
–
–
0
0
0
1
0
0
1
1
–
–
(Reserved)
–
–
–
(Reserved)
–
47
–
IOAPIC
–
Clock Output Disable
(Reserved)
Low
–
Active
–
–
–
(Reserved)
–
–
46
2
REF1
REF0
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
Data Byte 6
7
6
5
4
3
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
Rev 1.0,November 21, 2006
Page 7 of 13