W144
Table 4. Byte Writing Sequence (continued)
Byte
Sequence
Byte Name
Data Byte 0
Bit Sequence
Byte Description
4
5
Refer to Table 5
The data bits in Data Bytes 0–7 set internal W144 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 5, Data Byte Serial Configuration Map.
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
6
7
8
9
10
11
Writing Data Bytes
Table 6 details additional frequency selections that are
available through the serial data interface.
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0-7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
–
–
–
–
–
–
–
–
(Reserved)
SEL_2
–
–
0
0
–
–
–
–
–
–
See Table 6
See Table 6
See Table 6
5
SEL_1
0
4
SEL_0
0
3
Hardware/Software Frequency Select
SEL_3
Hardware
Software
0
2
See Table 6
0
1–0
Bit 1Bit 0Function (See Table 7 for function details)
00Normal Operation
01(Reserved)
00
10Spread Spectrum On
11All Outputs Three-stated
Data Byte 1
7
6
5
4
3
2
1
0
–
–
–
(Reserved)
–
–
–
0
0
0
0
1
0
1
1
–
(Reserved)
–
–
–
–
–
(Reserved)
–
–
(Reserved)
–
–
40
–
SDRAM_F
–
Clock Output Disable
(Reserved)
Low
–
Active
–
43
44
CPU1
CPU_F
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
Rev 1.0,November 21, 2006
Page 6 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
