欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY2SSTV857ZI-27 参数 Datasheet PDF下载

CY2SSTV857ZI-27图片预览
型号: CY2SSTV857ZI-27
PDF下载: 下载PDF文件 查看货源
内容描述: 差分时钟缓冲器/驱动器DDR333 / PC2700兼容 [Differential Clock Buffer/Driver DDR333/PC2700-Compliant]
分类和应用: 驱动器双倍数据速率PC时钟
文件页数/大小: 8 页 / 134 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第1页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第2页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第3页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第4页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第5页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第6页浏览型号CY2SSTV857ZI-27的Datasheet PDF文件第8页  
CY2SSTV857-27  
AC Electrical Specifications (AVDD = VDDQ = 2.5V 5%, TA = 0°C to +85°C)(continued)[9, 10]  
Parameter  
Description  
Output Enable Time[12]  
(all outputs)  
Condition  
Min.  
Typ.  
Max.  
Unit  
tPZL, tPZH  
3
25  
ns  
tPLZ, tPHZ  
Output Disable Time[12]  
(all outputs)  
3
8
ns  
tCCJ  
Cycle to Cycle Jitter [10]  
Half-period jitter[10, 13]  
f > 66 MHz  
–75  
–100  
1.5  
75  
100  
7.5  
7.5  
100  
50  
ps  
ps  
ns  
ns  
ps  
ps  
tjit(h-per)  
f > 66 MHz  
t
t
PLH(tPD)  
PHL(tPD)  
Low-to-High Propagation Delay, CLK to Y  
High-to-Low Propagation Delay, CLK to Y  
Any Output to Any Output Skew[14]  
Phase Error[14]  
Test Mode only  
3.5  
3.5  
1.5  
tSK(O)  
tPHASE  
–50  
Notes:  
12. Refers to transition of non-inverting output.  
13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other.  
14. All differential input and output terminals are terminated with 120:/16 pF, as shown in Figure 5.  
Rev 1.0,November 21, 2006  
Page 7 of 8