CY2SSTV857-27
Absolute Maximum Conditions[2]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply:................................................3.5V
VSS < (Vin or Vout) < VDDQ
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDDQ).
DC Electrical Specifications (AVDD = VDDQ = 2.5v 5%, TA = 0°C to +85°C) [3]
Parameter
VDDQ
VIL
Description
Supply Voltage
Condition
Min.
Typ.
Max.
2.63
Unit
V
Operating
PD#
2.38
2.5
Input Low Voltage
0.3 × VDDQ
V
VIH
Input High Voltage
Differential Input Voltage[4]
0.7 × VDDQ
0.36
V
VID
CLK, FBIN
Differential Input Crossing Voltage[5] CLK, FBIN
VDDQ + 0.3
V
VIX
(VDDQ/2) –
0.2
VDDQ/2 (VDDQ/2)+
0.2
V
IIN
Input Current [CLK, FBIN, PD#]
Output Low Current
VIN = 0V or VIN = VDDQ
–10
26
10
µA
mA
mA
V
IOL
VDDQ = 2.375V, VOUT = 1.2V
VDDQ = 2.375V, VOUT = 1V
VDDQ= 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
35
–32
0.6
IOH
Output High Current
–28
VOL
VOH
VOUT
VOC
Output Low Voltage
Output High Voltage
Output Voltage Swing[6]
Output Crossing Voltage[7]
1.7
1.1
V
VDDQ – 0.4
V
(VDDQ/2) –
0.2
VDDQ/2 (VDDQ/2)+
0.2
V
IOZ
High-Impedance Output Current
Dynamic Supply Current[8]
PLL Supply Current
VO = GND or VO = VDDQ
All VDDQ, FO = 170 MHz
VDDA only
–10
10
µA
mA
mA
µA
IDDQ
IDD
235
9
300
12
IDDS
Standby Supply Current
PD# = 0 and CLK/CLK# < 10
MHz
100
Cin
Input Pin Capacitance
4
pF
AC Electrical Specifications (AVDD = VDDQ = 2.5V 5%, TA = 0°C to +85°C) [9, 10]
Parameter
fCLK
Description
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Duty Cycle[11]
Condition
Min.
60
Typ.
Max.
200
60
Unit
MHz
%
AVDD, VDDQ = 2.5V r 0.2V
tDC
40
tLOCK
DTYC
100
50.5
51
Ps
60 MHz to 100 MHz
101 MHz to 170 MHz
20%–80% of VOD
49.5
49
1
50
%
%
tsl(o)
Output Clocks Slew Rate
2
V/ns
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary
input level. See Figure 6.
5. Differential cross-point input voltage is expected to track V
6. For load conditions see Figure 6.
and is the voltage at which the differential signal must be crossing.
DDQ
7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120: resistor. See Figure 6.
8. All outputs switching load with 14 pF in 60: environment. See Figure 6.
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down
spread or –0.5%.
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
where the cycle time(tC) decreases as the frequency goes up.
/t ,
C
WHC
Rev 1.0,November 21, 2006
Page 6 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
