CY2SSTU877
CLKT/CLKC
CLKT
CLKC
Figure 8. Output Enable and Disable Times
CLKT
CLKC
Figure 9. Input/Output Slew Rates
CARD
VIA
Bead
R1
AVDD
VDDQ
GND
ꢀ:
2200 pF
0603
0.1 µF
4.7 pF
1206
PLL
0603
AGND
CARD
VIA
Figure 10. AVDD Filtering[3,4,5]
Ordering Information
Part Number
Package Type
Product Flow
Lead-free and ROHS Compliant
CY2SSTU877BVXC-32
CY2SSTU877BVXC-32T
CY2SSTU877BVXI-32
52-pin VFBGA for DDR400
52-pin VFBGA for DDR400 – Tape& Reel Commercial, 0q to 70qC
52-pin VFBGA for DDR400 Industrial, –40q to 85qC
52-pin VFBGA for DDR400 – Tape& Reel Industrial, –40q to 85qC
52-pin VFBGA for DDR533 Commercial, 0q to 70qC
52-pin VFBGA for DDR533 – Tape& Reel Commercial, 0q to 70qC
52-pin VFBGA for DDR533 Industrial, –40q to 85qC
52-pin VFBGA for DDR533 – Tape& Reel Industrial, –40q to 85qC
Commercial, 0q to 70qC
CY2SSTU877BVXI-32T
CY2SSTU877BVXC-43
CY2SSTU877BVXC-43T
CY2SSTU877BVXI-43
CY2SSTU877BVXI-43T
Notes:
3. Place the 2200-pF capacitor close to the PLL.
4. Use a wide trace for the PLL analog power and ground. Connect PLL & Caps to AGND trace & connect trace to one GND via (farthest from PLL).
5. Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.9 ohm DC max, 600 ohms@100 MHz).
Rev 1.0,November 21, 2006
Page 7 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
