CY2SSTU877
AC Timing Specifications
Parameter
[1,2]
Description
Conditions
Min.
125
250
40
48
–
Max.
500
500
60
Unit
MHz
MHz
%
FCLK
Clock Frequency (Max)
Clock Frequency (Application)
Input Duty Cycle
Room temp and nominal VDDQ
Room temp and nominal VDDQ
TDC
TODC
TLOCK
TOENB
TODIS
Output Duty Cycle
52
%
PLL Lock Time
15
Ps
Output Enable Time
Output Disable Time
OE to any CLKT/ CLKC[0:9]
OE to any CLKT/ CLKC[0:9]
–
8
ns
–
8
ns
Tjitt (cc)
Cycle-to-cycle jitter
Period jitter
–40
–30
–45
–60
–50
–40
–
40
30
45
60
50
40
40
4
ps
ps
Tjit (Period)
Tjit (H-Period)
Half Period Cycle-to-cycle jitter
Above 270 MHz
Below 270 MHz
ps
ps
T(I)
Static Phase Offset
Dynamic Phase Offset
Clock Skew
Average 1000 cycles
ps
T(I)DYN
TSKEW
SLR(O)
ps
ps
Output Slew Rate
CLKT/ CLKC[0:9], FB_OUTT,
FB_OUTC
1.5
V/ns
SLR(I)
Input Slew Rate
CLK_INT, CLK_INC, FB_INT,
FB_INC
1
4
V/ns
V/ns
OE
0.5
Figure 1. Test Loads for Timing Measurement
Notes:
1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for
low speed system debug).
2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.
Rev 1.0,November 21, 2006
Page 4 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
