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CY2SSTU877BVXI-32T 参数 Datasheet PDF下载

CY2SSTU877BVXI-32T图片预览
型号: CY2SSTU877BVXI-32T
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V , 500MHz的10 -输出符合JEDEC标准零延迟缓冲器 [1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer]
分类和应用: 逻辑集成电路驱动
文件页数/大小: 8 页 / 136 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2SSTU877  
Pin Description  
Pin No.  
Name  
Description  
Ground for 1.8V analog supply  
1.8V analog supply  
G1  
AGND  
AVDD  
H1  
E1, F1  
E6, F6  
H6, G6  
CLK_INT, CLK_INC Differential clock input with a (10K–100K:) pull-down resistor  
FB_INT, FB_INC  
Feedback differential clock input  
Feedback differential clock output  
FB_OUTT,  
FB_OUTC  
B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, GND  
J5  
Ground  
F5  
D5  
OE  
OS  
Output enable (ASYNC) for CLKT[0:9] and CLKC [0:9]  
Output Select (Tied to GND or VDDQ)  
1.8V supply  
D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 VDDQ  
A2, A1, D1, J1, K3, A5, A6, D6, J6, K4,  
A3, B1, C1, K1, K2, A4, B6, C6, K6, K5  
CLKT [0:9]  
CLKC [0:9]  
Buffered output of input clock, CLK  
Buffered output of input clock, CLK  
Table 1. Function Table  
Inputs  
Outputs  
AVDD  
GND  
GND  
GND  
GND  
OE  
H
OS  
X
CLK_INT CLK_INC  
CLKT  
CLKC  
FB_OUTT FB_OUTC  
PLL  
L
H
L
H
L
L
H
H
L
L
H
L
H
L
Bypassed/Off  
Bypassed/Off  
Bypassed/Off  
Bypassed/Off  
H
X
L
H
H
L
Lz  
Lz  
H
L
L
L
H
Lz,CLKT7  
Active  
Lz,CLKC7  
Active  
H
VDD  
VDD  
L
L
H
L
L
H
L
Lz  
Lz  
L
H
L
On  
On  
H
Lz,CLKT7  
Active  
Lz,CLKC7  
Active  
H
VDD  
VDD  
VDD  
X
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
L
L
H
H
L
On  
On  
Off  
L
Lz  
Lz  
Lz  
Lz  
H
H
Reserved  
Recommended Operating Conditions  
Parameter  
Description  
Condition  
Min.  
0
Max.  
70  
Unit  
°C  
TA (Com.)  
Ambient Operating Temp  
VDD, AVDD Operating Voltage  
1.7  
1.9  
V
Rev 1.0,November 21, 2006  
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