CY28RS400
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
Description
0
1
Reserved
Reserved
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
CLKREQ#
CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
6
5
4
3
2
1
0
0
1
0
1
1
1
1
CPU
SRC
CPU pd drive mode
0 = CPU clocks driven when power down, 1 = CPU clocks tri-state
SRC pd drive mode
0 = SRC clocks driven when power down, 1 = SRC clocks tri-state
CPU
CPU_STOP# drive mode
0 = CPU clocks driven , 1 = CPU clocks tri-state
CPU2
CPU1
CPU0
Reserved
Allow control of CPU2 with CPU_STOP#
0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP#
Allow control of CPU1 with CPU_STOP#
0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP#
Allow control of CPU0 with CPU_STOP#
0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP#
Reserved
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6
5
4
3
2
0
0
0
0
0
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1
0
1
1
Reserved
Reserved
Reserved
Reserved
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ#1 control
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
6
0
SRC[T/C]4
SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
Rev 1.0,November 22, 2006
Page 6 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
