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CY28RS400OCT 参数 Datasheet PDF下载

CY28RS400OCT图片预览
型号: CY28RS400OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为ATI RS400芯片组 [Clock Generator for ATI RS400 Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 18 页 / 179 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28RS400  
Pin Description  
Pin No.  
Name  
Type  
Description  
47,46,43,42,  
41,40  
CPUT/C[2:0]  
O, DIF Differential CPU clock output.  
Intel Type-X buffer.  
50  
PCI0/409_410  
I/O, 33 MHz clock output/CPU Frequency table Select  
PD Intel Type-5 buffer.  
0 = 410 frequency select table  
1 = 409 frequency select table.  
This has an internal pull-down  
37  
IREF  
REF0/ FSA  
REF1/FSB  
REF2  
I
A precision resistor attached to this pin is connected to the internal current reference.  
54  
I/O,SE, 14.318 MHz REF clock ouput/ CPU Frequency Select. Intel£ Type-5 buffer.  
I/O, SE 14.318 MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer.  
O, SE 14.318 MHz REF clock ouput. Intel Type-5 buffer.  
53  
52  
7
SCLK  
I,PU SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down.  
I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down.  
8
SDATA  
27, 28, 30, 29  
SRCST/C[1:0]  
O, DIF DifferentialSelectableSerialreferenceclock. IntelType-Xbuffer. Includesoverclock  
support through SMBUS  
12, 13, 16,  
17, 18, 19,  
22, 23, 24, 25  
,34,33  
SRCT/C[5:0]  
O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer.  
10,11  
CLKREQ#[0:1]  
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard  
PD specification. These pins have an internal pull-down.  
0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled  
4
6
USB_48  
O, SE 48 MHz clock output. Intel Type-3A buffer.  
VTT_PWRGD#/PD  
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,  
PD FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin  
becomes a realtime input for asserting power down (active high)  
48  
CPU_STP#  
I, PU 3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned  
off two cycles after assertion of this pin  
9
FSC  
I
3.3V LVTTL input. CPU Clock Frequency Select  
3
VDD_48  
PWR 3.3V power supply for USB outputs  
PWR 3.3V power supply for CPU outputs  
PWR 3.3V power supply for PCI outputs  
PWR 3.3V power supply for REF outputs  
PWR 3.3V power supply for SRC outputs  
PWR 3.3V power supply for SRC outputs  
PWR 3.3V power supply for SRCS outputs  
PWR 3.3V Analog Power for PLLs  
GND Ground for USB outputs  
45  
VDD_CPU  
VDD_PCI  
VDD_REF  
VDD_SRC  
VDD_SRC1  
VDD_SRCS  
VDDA  
51  
56  
14, 21  
35  
32  
39  
5
VSS_48  
44  
VSS_CPU  
VSS_PCI  
VSS_REF  
VSS_SRC  
VSS_SRC1  
VSS_SRCS  
VSSA  
GND Ground for CPU outputs  
49  
GND Ground for PCI outputs  
55  
GND Ground for REF outputs  
15, 20, 26  
GND Ground for SRC outputs  
36  
31  
38  
1
GND Ground for SRC outputs  
GND Ground for SRCS outputs  
GND Analog Ground  
XIN  
I
14.318 MHz Crystal Input  
14.318 MHz Crystal Output  
2
XOUT  
O
Rev 1.0,November 22, 2006  
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